Unleashing the Power of Embedded DRAM

Embedded DRAM technology offers many advantages in System On Chip products. Computing applications demand memory with low latency and zero soft error rate. Graphics and networking need high bandwidth. Mobile applications require extremely low power. All applications benefit from the high density afforded by embedded DRAM technology. A single DRAM architecture cannot provide an optimal solution across the full range of applications. This paper describes in detail the advantages of embedded DRAM technology over external memory and embedded SRAM, and presents three 90nm embedded DRAM architectures optimized for specific applications. Embedded DRAM Value Proposition DRAM technology offers the highest density random access memory due to a simple 1T1C structure consisting of a single access transistor and a single storage capacitor. Typical 90nm embedded DRAM processes offer cell sizes in the range of 0.2?m2. In contrast, 90nm SRAM cells typically occupy around 1.0?m2 due to a more complex 6T structure comprised of cross-coupled latch and dual access devices. Taking into account the more extensive peripheral circuitry associated with DRAM, the overall density of a completed embedded DRAM marcocell is about four times that of the SRAM alternative. In DRAM a read operation is destructive since the charge on the storage capacitor is shared with the larger bitline capacitance. This data must be sensed and fully restored to the cell capacitors during each memory cycle. In a typical DRAM row operation, many thousands of bits are sensed and are available for use on-chip. In commodity DRAM, only a small fraction of the bits which are sensed in each row cycle are made available off-chip. In a 256M DDR2 SDRAM with a x16 400Mb/s/pin interface for example, 8192 High Bandwidth High Speed Low Power Capacity 16Mb 2Mb 8Mb Interface 2048bit synchronous 128bit synchronous 64bit asynchronous Array Size 256r x 1024c 128r x 256c 256r x 512c Page Size 8192bit 512bit 512bit # of Banks 2 banks 16 banks 1 bank Macro Size 6.0mm2 1.4mm2 3.3mm2 Density 2.69Mb/mm2 1.32Mb/mm2 2.45Mb/mm2 Data Rate 500MHz 1GHz 166MHz Cycle Time 16ns 4ns 6ns Bandwidth 128GB/s 16GB/s 1.33GB/s Supply 1.2v 1.2v 1.0v (0.7v in standby) Active Power 1.2W 220mW 25mW Standby Power 1mW 66mW 35μW Table 1. Summary of Optimized 90nm Embedded DRAM Macrocells Copyright © 2005 Design And Reuse S.A. All rights reserved.